Metrology and Inspection Challenges at 5nm and Beyond

The Scaling Technologies TechXPOT at this year’s SEMICON West (Scaling Every Which Way! – Thursday, July 12, 2:00pm-4:00pm) will explore traditional scaling as the industry marches toward 3nm and beyond, as well as technologies that enable 3D architectures, die stacking, and interconnect scaling. The session will also provide an update on how the various players (foundry, IDM, fabless, and application developers) are jockeying for innovation leadership. As a prelude to the event, SEMI asked Priya Mukundhan, director, Technology Development and Applications, at Rudolph Technologies, and a speaker at the TechXPOT, to provide her insights into challenges associated with metrology and inspection.

For a full list of speakers and program agenda, visit

SC West Priya Mukundhan

Priya Mukundhan, director, Technology Development and Applications, Rudolph Technologies

SEMI: What are the key challenges that need to be addressed to provide the kind of metrology and inspection solutions that will be needed by the industry as scaling – in all its forms (e.g., traditional, 3D ICs, interconnect, and different transistor architectures) – is pursued at 5nm and then at 3nm? 

Priya Mukundhan: With respect to metrology needed to scale FinFETs, the following will be key:


  • Gate critical dimension (CD) at the fin sidewall, gate height, gate profile
  • Fin CD, height and profile
  • Dopant profiles
  • Stress measurement in the fin
  • Composition in thin film and interface

These challenges are currently being handled using in-line CD solutions, CD scanning electron microscopy (CD-SEM) and CD atomic force microscopy (CD-AFM), along with optical critical dimension (OCD) measurements. There is no single technology that can take all of these measurements, and determining the right solution is application-dependent[1].

Issues associated with inspection and scaling include the following:

  • Bright-field inspection lacks the sensitivity to detect defects smaller than those found at the 20nm node
  • Detecting defects that are 5nm or smaller is achieved using electron beam inspection tools, but these single-electron beam inspection systems are prohibitively slow and cannot meet the high-volume manufacturing (HVM)         requirements for defect inspection
  • Buried defects
  • Void detection in 3D SiP structures, front and backside inspection
  • Sidewall crack detection in packaging

SEMI: Can you provide a summary of the R&D roadmap for metrology/inspection tools that you see emerging in order to get to 3nm? 

PM: Hybrid metrology is currently in use, especially for CD metrology. To support the development efforts, techniques that provide complementary information as well as those that eliminate uncertainties will be required. 

Rudolph Tech SC West PQ

Researchers at imec[2] have started exploring technology combinations to gain insight into how new structures function. Some of the findings in imec’s study include the following:

  • The combination of transmission electron microscopy (TEM) and scanning probe microscopy (SPM) provides a unique approach of imaging combined with a functional analysis capability
  • In situ SPM could potentially determine composition (SIMS) as well as functional properties (electrical)
  • Fast Fourier transform scanning spreading resistance microscopy (FFT-SSRM) is a novel technique that measures carrier profiles in semiconductors. This overcomes the current SSRM limitations of signal distortions due to parasitic  resistances while measuring on small volumes such as FinFET and nanowires
  • Multi-electron beam inspection can be used for HVM for sensitivity to smaller

SEMI: How will metrology and inspection be impacted beyond 3nm? What kinds of tools will be needed by that point in time?

PM: There are several different transistor options that have been identified by leading edge wafer fabs and consortia looking beyond the 5nm node roadmap[3,4]. Some of the options on the table include the following: 

1) Extension of the current FinFET in the form of gate-all-around FET

2) Creating them with new materials by adding ferroelectrics (e.g., negative capacitance FET, or NC-FET)

3) Complementary FET

4) Vertical nanowires and nanosheet FETs

These possibilities bring new challenges and require characterization at the material level. Also, the industry as a whole will have to redefine what it means to do composition at the nanometer level. This could be the beginning of a trend towards array-based metrology, i.e., measurements on an array of devices to gather statistically significant data[2].

Rudolp Tech PQ 2

Regarding metrology needs at 3nm, it is too early to determine what kind of tools would be needed only for R&D and how many of them would need to be extended to high-volume manufacturing (HVM). From an inspection perspective, there will be a continued migration towards computer aided design (CAD)-based inspection, as well as having the ability to deal with large image data sets (petabyte, big data). Furthermore, inspection algorithms should be improved, along with better staging for better image stitching.


  1. Bunday, E. Solecky, A. Vaid, A. F. Bello, X. Dai, “Metrology capabilities and needs for 7nm and 5nm logic nodes,” Proc. Of SPIE, Vol. 10145, 101450G, pp. 1-41, 2017.
  2. Imec roadmap and imec magazine.
  3. Intel roadmap.

Debra Vogler, SEMI

Topics: SEMICON West , 3nm , 5nm , metrology , finFET , imec , Rudolph Technologies , inspection